1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a technology of a buffer control for a refresh operation in a semiconductor memory device.
2. Description of the Related Art
Recently, research into a technology for reducing current consumption of a semiconductor memory device has been variously conducted. Particularly, as a rapid increase in demands for mobile devices such as mobile phones or personal digital assistants (PDAs), an effort for reducing current consumption of a semiconductor memory device (for example, a dynamic random access memory (DRAM)) mounted in such mobile devices has been continued. According to one of various methods for reducing the current consumption of the semiconductor memory device, reducing the current consumption for a refresh operation in the semiconductor memory device is an issue.
Among various kinds of semiconductor memory devices, the DRAM has characteristics that data stored in a memory cell is lost according to the passage of time, unlike a static random access memory (SRAM), a flash memory, or the like. In order to substantially prevent this, an operation, in which information stored in the cell is rewritten from an exterior in a given cycle, is performed, and such a series of operations are called the refresh operation. All word lines in the DRAM have to be activated at least once in a retention time, and data corresponding to the activated word line are sensed and amplified in the refresh operation. The retention time indicates a time for which data is written in a cell and then may be substantially maintained in the cell without the refresh operation.
The refresh operation is classified into an auto-refresh operation (or an auto-refresh mode), which is performed in a normal mode, and a self-refresh operation (or a self-refresh mode), which is performed in a power-down mode (a state in which a clock enable signal CKE has been deactivated).
FIG. 1 is a timing diagram for explaining a self-refresh operation.
A self-refresh mode is entered when, in a state in which a clock enable signal CKE has been deactivated, a combination of signals input by a plurality of command buffers (not illustrated in FIG. 1) corresponds to a refresh command AREF.
A self-refresh signal SREF defines a period that the elf-refresh mode is performed, and a refresh signal REF is a signal indicating that refresh is being internally performed (that is, a signal for controlling a word line to be activated for the refresh operation). A clock CK is a clock signal with which operations of the DRAM is synchronized. The self-refresh signal SREF is activated when a semiconductor memory device enters the self-refresh mode (SRE), and is deactivated when the semiconductor memory device exits from the self-refresh mode (SRX).
As illustrated in FIG. 1 there exist a case in which a word line is activated before the self-refresh mode is completed and the activation of the word line may be completed after the self-refresh mode is completed. That is, although the self-refresh mode has been completed, the refresh operation, which has been internally started before the self-refresh mode is completed, may be continued after the self-refresh mode is completed.
Since the semiconductor memory device does not receive a plurality of commands and a plurality of addresses from an exterior when performing the refresh operation, it is not necessary to use a plurality of command buffers for receiving the plurality of commands and a plurality of address buffers for receiving the plurality of addresses. Since these buffers continuously consume current in an enabled state, a technology of activating or deactivating the plurality of command buffers and the plurality of address buffers at a proper time according to auto-refresh and self-refresh is needed, in order to possibly reduce current consumption of the semiconductor memory device.